In a conventional integrated circuit design approach for analog and radio frequency (RF) applications, the front-end design is separated from the back-end design. A front-end circuit designer would hand off the design to a back-end circuit designer to create the layout. As a result, the parasitic effects from the layout are not taken into account in the front-end design process. This conventional design approach is particularly challenging for analog and RF circuit designs. For example, an RF design is sensitive to the accuracy of interconnect parasitic information. The capacitance, inductance, and resistance of wires between devices may have a significant impact on the electrical performance of the RF circuit. Further, even when parasitic effects are taken into account in the front-end design by using a prototype layout created during the early design process, as the device sizes are updated during the sizing process, the layout also needs to be updated to reflect the new set of device sizes. This in turn affects the layout parasitic information, which may lead to multiple iterations between the processes of circuit sizing and layout and may prolong the product development schedule. Therefore, there is a need for a new set of design tools that can effectively communicate parasitic information between the circuit sizing process and the circuit layout process.
In addition, after the initial circuit design and layout are completed, there are situations where the design and layout may need to be tweaked. This may be due to an Engineering Change Order (ECO), where the top-level design specifications and constraints may have changed after the design is completed. For instance, the new requirement may demand higher gain for the circuit. As a result, the sizes of some transistors in the circuit may need to be adjusted to meet the new specifications. This impacts not only the design, but also the layout, since a change in design affects the device sizes in the layout, which in turn affects the layout parasitic information and therefore the circuit performances. Under this scenario, it is time-consuming to re-design the entire circuit and create a new layout. To address this issue, one approach is to tweak some of the device sizes in the existing design and/or to tweak some aspects of the layout such as the device locations. This approach is referred to as circuit and layout tuning. Most commonly used techniques for circuit and layout tuning today are manual, whereby certain aspects of the circuit are adjusted manually. There is no direct communication between the sizing tool and the layout tool regarding the parasitic effects as a result of tuning the circuit. For RF and analog circuits, this approach is quite cumbersome, because the analog and RF circuits are more sensitive to parasitic effects.
Therefore, there is a need for an integrated and automated circuit sizing and layout tool with circuit tuning capability for designing analog and RF circuits.